1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device with multiple channels in which a gate electrode layer partially encompasses a channel layer and a method of fabricating the same.
2. Description of the Related Art
As the application fields of semiconductor devices have been expanded, the demand for highly integrated and high-speed semiconductor devices continues to rapidly increase. The recent large integration scale of semiconductor devices has resulted in a significant decrease in the design rule of devices. As a result, the channel length and the channel width of a field effect transistor (FET) continues to decrease as well. A decreased channel width can cause the well-known short channel effect to occur, in which the electric potential of the device source region and drain region have a severe impact on the channel layer. For a transistor using a shallow trench device isolation layer, a narrow channel decreases the threshold voltage level. Therefore, various types of FETs have been proposed to reduce the short channel effect and/or the narrow channel effect.
One proposed FET is a gate-all-around transistor (GAAT) in which a channel layer, such as a nanowire, encompasses the gate electrode layer. Recently, a sacrificial layer, for instance, a silicon germanium (SiGe) layer has been used for GAAT-type devices.
However, in a conventional GAAT, when the gate electrode layer is trimmed, an upper portion and a lower portion of the gate electrode layer have a different thickness. Specifically, the upper portion of the gate electrode layer is thinner than the lower portion thereof, and thus, the gate electrode layer becomes non-uniform. In addition, any sacrificial layer remaining on source and drain regions often causes an incidence of leakage current in which current, in general, leaks toward the lateral sides of source and drain regions or toward a semiconductor substrate. Furthermore, an unintended parasitic channel may be formed on the gate electrode layer and the semiconductor substrate, and the unintended parasitic channel can result in degradation of material properties of the semiconductor devices.